— Bridging Serial & TCP/IP Worlds

(Module 3 · Modbus TCP/IP)

Ambition for this chapter: Build the best single source on earth for everything that happens inside a Modbus gateway—PCB traces to Linux kernel queues, RTU-to-TCP buffering algorithms, session tables, security policy engines, latency math, field wiring mistakes, and laboratory verification. By the end you will be able to design, select, configure, harden, tune, and troubleshoot gateways that keep 24 × 7 plants running while feeding millisecond data to cloud analytics.


Chapter Navigation

§TopicYou’ll master
9.1Gateway taxonomyTransparent, intelligent, tag-mapping, hybrid
9.2Hardware architectureMCU vs Linux-SBC, PHYs, isolation, watchdogs
9.3Serial-side engineState machine, T3.5 scheduler, DMA, CRC logic
9.4TCP-side engineSession table, MBAP mapping, flow-control, keep-alive
9.5Routing & Unit-ID logicOne-to-one, many-to-one, offset maps, NAT-like rewrite
9.6Buffering & QoS algorithmsStore-&-forward, credit-based, priority, fairness
9.7Latency & throughput mathQueue theory, poll budgets, worst-case jitter calc
9.8Configuration deep diveBaud discovery, timeouts, serial break detect, VLANs
9.9Reliability patternsDual-port redundancy, hot-standby, watchdog recovery
9.10Security layerACLs, function-code filtering, TLS termination, RBAC
9.11Management & observabilitySNMP/OID map, Syslog, Prom-exporter, OTA strategy
9.12Lab: build a DIY gatewaySTM32 + FreeRTOS + LwIP source code & BOM
9.13Field diagnostics cookbookLogic-scope, Wireshark, smoke-test script
9.14Case studiesSolar farm, water SCADA, brown-field steel mill
9.15Best-practice tear-out sheet20 rules to pin on the control-room wall

(Diagram placeholders [Fig-9-x]; code listings Listing x; hands-on labs Lab x.)


9.1 Gateway Taxonomy

TypeBehaviourTypical productsUse-case
TransparentSimply re-encapsulates bytes; no register awarenessRS-232-to-TCP “device servers”Laptop commissioning, lab hacks
Intelligent RTU/TCPParses MBAP, enforces timing, auto-CRCMoxa NPort 5000, HMS Anybus10-30 slaves / loop, plant control
Tag-mapping / protocol converterExposes HTTP/REST, MQTT, OPC UA; caches register mapSiemens IoT2040, Kepware EdgeIIoT, cloud dashboards
HybridMix of above with scripting (Lua, Python)Red Lion FlexEdgeCustom logic, KPI computation

9.2 Hardware Architecture

9.2.1 Block diagram – [Fig-9-1]

ARM Cortex-A7 SoC · DDR3 512 MiB · eMMC 8 GiB · 3 × RS-485 half-duplex (isolated) · 2-port GbE switch PHY · TPM 2.0

9.2.2 Key design calls

SubsystemBest-practice
TransceiversISO3082 / ADM2587E (500 kBd, ±15 kV IEC ESD)
Isolation3 kVrms digital isolators AND isolated DC/DC for each port
ClockOne 26 MHz TCXO → reduces baud drift < 75 ppm across −40 – +85 °C
WatchdogDual — MCU IWDT (1 s), external windowed (Renesas)
PowerSurge tested to IEC 61000-4-5, common-mode choke on RJ-45

9.3 Serial-Side Engine

9.3.1 RTU state machine (per port)

IDLE → COLLECT → VERIFY_CRC → WAIT_PROC → TX_RESP → IDLE
  • Implementation in 700 B Flash (C), ISR on UART RX using DMA circular buffer.
  • Gap detector: 16-bit timer reset on every RX interrupt; if count ≥ T3.5 char → frame complete.

9.3.2 T3.5 Scheduler Strategies

StrategyProsCons
Static 3.5×TcharSimplicityInefficient at mixed baud
Adaptive idle detectHandles slaves that echoAdds edge cases
Token bucketGuaranteed fairness when master writes constantlyComplex maths

9.4 TCP-Side Engine

ElementDetail
Session table128 entries ⇒ 128 × (4 B IP + 4 B idle_ts + 2 B port + flags) ≈ 2 kB
Concurrent socketsEpoll loop, edge-triggered, 4 kvec batch sends
Aggressive FIN recycleTime-wait buckets < 5 k using net.ipv4.tcp_tw_reuse=1

9.4.1 Keep-alive matrix

LinkTCP_KEEPIDLETCP_KEEPINTVLNAT idle safe
LAN60 s30 sn/a
LTE NAT20 s10 s45 s
Satellite120 s60 s240 s

9.5 Routing & Unit-ID Logic

9.5.1 One-to-one map (simplest)

Unit-IDRS-485 Slave AddressPortComment
1-31=COM1Classic loop

9.5.2 Offset map

Useful when two loops use same IDs.

Unit-ID 1-31  → COM1 addr 1-31
Unit-ID 101-131 → COM2 addr 1-31

9.5.3 NAT-like rewrite

Rewrite Unit-ID on fly; table stored in SQLite, hot-reload via REST.


9.6 Buffering & QoS Algorithms

9.6.1 Store-&-Forward vs Cut-Through

ModeLatencyMemoryRisk
Store-&-ForwardDeterministic; queues until full responseNeeds (req+resp)RAM blow-up with 30 concurrent masters
Cut-ThroughLowest latency, bytes stream instantlyTinyCollapse if frame error mid-flight

9.6.2 Credit-based fairness – [Fig-9-2]

Each TCP client has credits (#frames). Gateway grants 1 credit/frame, refills every poll cycle. Prevents SCADA historian flood starving HMI.


9.7 Latency & Throughput Math

9.7.1 Serial bottleneck formula

Tserial=(Lreq+Lresp+3.5+1.5)×11baudT_{\text{serial}} = \frac{(L_{req}+L_{resp}+3.5+1.5)\times 11}{\text{baud}}

9.7.2 Gateway overall

Tend-to-end=Ttcp rtt+Tqueue+TserialT_{\text{end-to-end}} = T_{\text{tcp\,rtt}} + T_{\text{queue}} + T_{\text{serial}}

Budget: keep Tqueue < 2×Tserial for smooth browsing.

[Fig-9-3] Heat-map of end-to-end latency for baud 9 600–115 k & poll depth 1–50.


9.8 Configuration Deep Dive

SettingDefaultField-tuned valueReason
Serial baud9 60038 4008× throughput, still noise-tolerant
Response timeout1 000 ms250 msModern PLC respond <100 ms
Retry count31Gateway handles, SCADA shouldn’t flood
Inter-char gapAutoStrict (T1.5)Weed out flaky slaves

9.9 Reliability Patterns

  1. Dual independent gateways — Each PLC connects to A & B; fail-over by TID-timeout.
  2. VRRP floating IP — Two gateways share virtual IP 10.0.30.100, premptive fail-back off.
  3. Edge watchdog — GPIO toggled by kernel thread; external WDT cuts power if no toggle 5 s.
  4. Ring buffer logging — 4 k latest frames in FRAM; survive power-fail for root-cause.

9.10 Security Layer

LayerControlExample implementation
NetworkVLAN 30, ACL permit SCADA_IP → 502Cisco ip access-group OT-ACL in
AppFunction-code allow-list (01-04)IPTables NFQUEUE + user-space filter
ProtocolTLS (MBSec draft2)OpenSSL server cert in TPM
AdminRBAC (viewer, engineer, admin)UI behind OAuth2

Function-code firewall – blocks FC05/06/15/16 from cloud analytics while allowing read-only.


9.11 Management & Observability

MetricOID / PrometheusThreshold
Serial Rx errorsgateway_serial_crc_errors_total>1/min triggers warn
CPU tempSNMP 1.3.6.1.4.1.2021.13.16.4.1.5>85 °C critical
Queue depth (max)gateway_queue_max_depth>8 frames indicates overload

OTA Upgrade pipeline: Signed image → SFTP to /update → A/B partition swap → auto-rollback on WDT.


9.12 Lab — Build a DIY Gateway

Hardware BOM

QtyPartRef
1STM32F429-DISC1MCU
1W5500 EthernetSPI-MAC
1ADM2587E iso-RS-485COM1

Software Stack

  1. FreeRTOS
  2. LwIP TCP/IP (raw API)
  3. TinyModbus (MIT) serial back-end
  4. Custom bridge task (priority 3)

Listing 3 Full source, 2 064 lines, available in Git repo.


9.13 Diagnostics Cookbook

SymptomToolDiagnostic stepsFix
Random CRC errors on all slavesLogic analyser on A/B linesSee missing bias, add 680 ΩWire
High TCP RTT spikesWireshark tcp.analysis.ack_rtt graphNODELAY offEnable
Queue overflowsgateway_queue_max_depth alarmIdentify abusive IPApply credit limit

9.14 Case Studies

9.14.1 50 MW Solar Farm

  • 72 combiner boxes (RS-485, 19 200 Bd) → 3 rugged Linux gateways → fibre VLAN → SCADA & cloud MQTT.
  • Redundancy: VRRP + PRP.
  • KPI: Mean poll 3.2 s for 4 500 registers. Outage 0.002 %.

9.14.2 Municipal Water SCADA

  • 25 bore-wells radio telemetered as Modbus ASCII → TCP gateway at control room.
  • Cut monthly leased-line fee 40 % vs legacy modem.

9.14.3 Brown-field Steel Mill

  • 1980s drives kept on 9600 Bd; gateway implements on-the-fly word-swap and tag alias table; cloud historian now reads energy KPIs without touching old PLC.

9.15 Best-Practice Tear-Out Sheet

  1. Bias & termination first, firmware second.
  2. Never mix write clients—use one master or locking.
  3. Size RS-485 loop ≤ 20 slaves @ 38k4; add bus repeaters for more.
  4. Always enable TCP_NODELAY on masters ≤ 100 ms cycle.
  5. Keep gateway queues bounded; back-pressure abusive SCADA.
  6. Implement FC allow-list; deny 05/06/15/16 from untrusted zones.
  7. Monitor crc_errors_total and queue depth; they reveal 80 % of issues.
  8. Use dual watchdogs (internal + external).
  9. Sign every OTA; auto-rollback on failure.
  10. Document Unit-ID ↔ physical device map in CMDB.

Assets to produce

IDAssetPurpose
Fig-9-1Gateway PCB blockVisual hardware grasp
Fig-9-2Credit-based fairness diagramQoS education
Fig-9-3Latency heat-mapDesign sizing
ListingsFull gateway sourceLearning & audit
Lab-scriptsWireshark + iperf test setValidation

What’s next?

With gateway internals mastered, Module 4 dives into the data flowing through them: Chapter 10 — Modbus Data Model: Coils, Inputs & Registers. We’ll map real-world sensors to 16-bit words, wrestle with one- vs zero-based notation, and build a register sheet that any commissioning tech can follow.

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